The ever increasing demands for more efficient power supplies and longer lasting battery-powered electronic devices have made efficiency in power management systems one of the most challenging areas for engineers. Thus, improving the characteristics of discrete power devices, such as power MOSFETs, which are used in power management systems, continue to push manufacturers to produce devices with lower ON-resistance, lower gate charge and higher current capability.
A process according to the present invention significantly reduces the size of the features in a power device, resulting in reduced ON-resistance, reduced gate charge, and increased current carrying capability. As a result, a device, such as a power MOSFET, produced according to the present invention can be used in high frequency, e.g. 1 MHz, applications without undue heat generation. Thus, devices produced according to the present invention exhibit improved characteristics for power conversion.
A power MOSFET produced according to an embodiment of the present invention is of a trench variety, in which the active region includes a plurality of trenches each supporting a gate structure and each formed in an epitaxial layer that is grown over a monolithic semiconductor substrate. Disposed around the active region of the device is a termination structure. The termination structure is formed in a recess around the active region and includes a layer of field oxide disposed on the surfaces of the recess, a conductive layer disposed on the field oxide and a low temperature oxide formed over the conductive layer. A contact layer may be formed over the low temperature oxide and connected to the conductive layer of the termination structure through the low temperature oxide.
The termination structure can significantly reduce the electrical field crowding at termination, thus eliminating the need for implanted guard rings without compromising the device breakdown voltage and ruggedness. Typical avalanche energy measured for this termination structure has been 1 J for a die in a DPAK.
The field oxide in the termination structure is grown using, for example, LOCOS process after the termination recess has been etched. Because the field oxide is below the top surface of the die, wafer planarity at active trench lithography stage is improved greatly. The much improved wafer surface planarity at trench lithography stage allows for further reduction of trench width by as much as 20%. This reduction in size makes it possible to, for example, increase the density of the trenches thus increasing channel density while keeping the gate charge low, especially the QGD and QSWITCH. To add to the performance of the device the depth of the channels may also be reduced.
A process according to the present invention includes forming source regions after high temperature steps have been carried out. As a result, the dimensions of the source regions can be minimized which allows for a reduction in the depth of the channel region and thus shorter channels in the device. The shorter channels in turn improve the ON-resistance of the device. In addition, shorter channels require a thinner epitaxial layer, as compared to prior art devices, thus reducing the cost of the device as well as further reducing the ON-resistance by shortening the common conduction region of the device.
A process according to the present invention include the following features: defining the termination recess and active area trenches with a nitride hard mask; implanting the channel dopants through a screen oxide into the epitaxial layer; forming a thick oxide at the bottom of the active area trenches; and source formation after formation of gate structures.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.